The pen/digitizer consists of an electromagnetic battery powered pen, an inductive receiving grid, and associated logic and firmware (Figure 7-1). The grid, located directly under the LCD panel, detects and determines the location of a 57.6 KHz signal emitted by the battery powered pen. The grid matrix is scanned and the information is digitized. The digitizer to system interface is handled in two stages: through an 8 bit multiplexed address/data bus using 8051-type handshake logic of the keyboard controller, and finally through control registers and a FIFO to the peripheral (ISA) bus. A special set of BIOS calls (firmware in ROM) are used to control the digitizer pen and initiate a pen driver. The driver (software) run by system processor interprets the digitizer data and controls how the data is displayed through the video subsystem. The digitizer hardware provides support of control points, which are relative to "hot keys" used on the keyboard. When the pen is detected in a control point, immediate action is initiated by the generation of an SMI, unless masked, and the overlay engine of the video subsystem generates a pop up (overlay) window that is used to control and display a system parameter. ILLUSTRATION OF Figure 7-1. Digitizer Subsystem Block Diagram The digitizer firmware uses a five byte data format (Figure 7-2) that contains pen proximity, pen control, and pen location (x/y coordinate) information. ILLUSTRATION OF Figure 7-2. Digitizer Data Format Digitizer data is handled by the FIFO as coordinate information packets. The size of a coordinate information packet is programmable from 1 to 32 bytes. The FIFO can hold 32 bytes and is circular in operation. Every time a complete packet is written into the digitizer FIFO, a "packet ready" interrupt (programmable to IRQ5, IRQ7, IRQ9, or IRQ15) will be generated and the system processor will service the interrupt by reading the packet bytes from the FIFO. When the system processor has read the last byte of a packet, the associated "packet ready" interrupt is cleared. While the microprocessor is reading packet bytes from the FIFO, the digitizer logic can be writing the next (succeeding) packet into the FIFO. If a succeeding packet is completely loaded into the FIFO before the system processor has finished reading the preceeding packet, the interrupt generated by the succeeding packet will be latched (held) until the preceeding packet(s) is processed and its interrupt(s) is cleared. Up to 31 "packet ready" interrupts may be latched by the digitizer control logic. ====== A special set of BIOS calls (firmware in ROM) are used to control the digitizer pen and initiate a pen driver. The driver (software) run by system processor interprets the digitizer data and controls how the data is displayed through the video subsystem. INT 15h, AH = E8h, AL = 10h - Enable/Disable Pen Device INT 15h, AH = E8h, AL = 10h enables the digitizer pen and sets the modes. In Tap mode, a packet of data is sent each time the pen tip switch changes state (pen is put down on the screen or taken up). In the Stream mode, pen data is sent continuously while within range of the grid. NOTE: In any case, pen data is sent only when the pen is within range of the grid. INPUT: AH = E8h AL = 10h BH = 00h, Disable pen device 01h, enable pen device BL = Modes: <0> = 0, Set tap mode - one packet of data is sent each time the pen tip changes state (pen is put down on screen or taken up) = 1, Set stream mode - pen data is sent continuously while in range) <1> = 0, Set non-incremental mode = 1, Set incremental mode <15..2> = 0's for future compatibility OUTPUT: AH = 00h, no error = 01h, Invalid function call = 02h, Invalid input = 03h, Interface error = 04h, Undefined = 05h, No far call installed error CF = 0, Successful completion; = 1, unsuccessful operation INT 15h, AH = E8h, AL = 11h, - Pen Device Driver Far Call Initialization INT 15h, AH = E8h, AL = 11h stores the location of the pen device driver entry point in the extend BIOS data area. INPUT: AH = E8h AL = 11h BX = Offset of device driver address ES = Code segment of device driver address OUTPUT: AH = 00h, no error = 01h, Invalid function call = 02h, Invalid input = 03h, Interface error = 04h, Undefined = 05h, No far call installed error CF = 0, Successful completion; 1, unsuccessful operation When called, the pen driver is provided with the following parameters: BX = Pen Status Flags: <0> = 1, Tip switch on (pen down) <1> = 1, Barrel switch on <7> = 1, Pen data is in range CX = X location DX = Y location INT 15h, AH = E8h, AL = 12h, - Get Pen Configuration Information INT 15h, AH = E8h, AL = 12h returns information on availability of the digitizer pen and how the digitizer is configured. INPUT: AH = E8h AL = 12h OUTPUT: AH = 00h, no error = 01h, Invalid function call = 02h, Invalid input = 03h, Interface error = 04h, Undefined = 05h, No far call installed error CF = 0, Successful completion; 1, unsuccessful operation BX = Pen information: <0> = 0, pen/digitizer not present; 1, pen/digitizer available <1> = 0, Text stretch not enabled; 1, text stretch enabled <2,3> = Reserved (00) <4..7> = IRQ 0-15 (0000 = IRQ0, 1111 = IRQ15) <8..15> = Reserved (0's) CX = Reserved (==>0) DX = Reserved (==>0) ECMOS byte 15h, <3,2>: 00 - IRQ9 01 - IRQ10 10 - IRQ11 11 - IRQ15 ======== The digitizer is controlled through registers described in this section. Some registers are dual ported, i.e., they can be addressed by the keyboard controller or by the system processor (I/O address). Other registers are addressed by either the processor or the keyboard controller. The register descriptions are in I/O (processor) address order, followed by registers that are accessed only by the keyboard controller. NOTE: Some registers control functions and set parameters that are unrelated to the digitizer. Packet Size Register, I/O Address 9Dh, Read/Write This register is used set the number of bytes in a coordinate information packet, i. e., the number of bytes that need to be written to the digitizer FIFO before generating a "packet ready" interrupt. I/O Address 9Dh, R/W Kybd Address 8027h, R/W BIT FUNCTION -------------- 7 FIFO Empty Flag 0 = FIFO not empty 1 = FIFO empty 6 FIFO Write Space 0 = Complete packet space available in FIFO 1 = Complete packet space not available in FIFO 5 FIFO Pointer Reset 0 = Normal operation 1 = FIFO R/W pointers reset to the top of FIFO and all pending/ latched FIFO interrupts cleared. 4..0 Packet Size (in decimal) of 1 to 31. A value of 0 is the same as a 1. Digitizer Data Register, I/O Address 9Eh, Read Only This 8 bit register is where the system processor reads data from the digitizer FIFO. As bytes are read, the read pointer is automatically incremented. When the programmed number of packet bytes have been read, the corresponding packet interrupt will be cleared. If an interrupt is pending (latched) at that time, it will generate a new interrupt. The system processor read pointer will automatically be reset to the top of the FIFO if bit <5> of the Packet Size Register is set and all pending interrupts will be cleared. Control Point Detect Register, I/O Address 9Fh, Read Only This 8 bit register is written with particular codes when the processor detects digitizer input within a pre-defined control point area on the digitizer grid. A write to this register by the 8051-type (keyboard) controller (writing to 8028h) will result in the generation of an SMI unless bit <0> of the External SMI Mask Register is cleared (0) to mask it. Control Point Data Register, I/O Address A0h, Read Only This 8 bit register is similar to the Control Point Detect Register previously described, and is used to pass Control Point control information to the system processor. A write to this register by the keyboard controller (writing to 8029h) does NOT automatically cause the generation of an SMI. Secondary System to Keyboard Controller Mailbox Data Register, I/O Address A1h, Read/Write This 8 bit register is used by the microprocessor to pass specific digitizer information to the keyboard controller (keyboard address 802Ah), and is similar to the Primary System to Keyboard mailbox register at keyboard address 8019h (read only). A write to this (A1h) register causes bit <6> of the INT0 Source Register to be set and, if unmasked, resulting in the INT0- signal to be toggled low. Mailbox Buffer Full/Empty Register, I/O Address A8h, Read Only This 8 bit register is used by the microprocessor and the keyboard controller (keyboard address 8038h) to determine when data has been read from various buffers as indicated in the box below. When a source writes to a buffer, that buffer's corresponding flag in this register is set. When the destination reads from that buffer, its corresponding flag in this register (if set) is cleared. I/O Address A8h, R/W Keyboard Address 8038h, R/W BIT FUNCTION --------------- 7..4 Reserved 3 Secondary System to Keyboard Buffer Flag: 0 = Buffer is empty (has been read) 1 = Buffer is full (has not been read) 2 Primary System to Keyboard Buffer Flag: 0 = Buffer is empty (has been read) 1 = Buffer is full (has not been read) 1 Keyboard to System Buffer Flag: 0 = Buffer is empty (has been read) 1 = Buffer is full (has not been read) 0 Control Point Data Register Flag: 0 = Buffer is empty (has been read) 1 = Buffer is full (has not been read) External SMI Source/Mask Registers, I/O Address 1465h/3865h, Read/Write These 8 bit registers control the generation of an SMI. The SMI can be generated by a number of actions including detection of the pen at a Control Point location (bit <0>). When the Control Point Detect Register has been written to by the 8051-type (keyboard) controller, bit <0> of the External SMI Source Register is set. If bit <0> of the External SMI Mask Register is 1 (unmasked value) then an SMI will be generated. A system processor write to the External SMI Source Register will always clear the register. A keyboard controller write to the External SMI Mask Register will always clear the register. I/O Address 1465h, R/W-Clear only Keyboard Address 8024h, R/W BIT FUNCTION -------------- 7 SMI REQ: 0 = No EXTSMI * pending 1 = EXTSMI * pending 6 Pop-Up Timeout: 0 = Timer has not expired 1 = Timer has expired 5 EBOX_ACT: 0 = No change in EBOX * input 1 = Transition in EBOX * input 4 KEY_SEQ: 0 = No sequence 1 = Sequence detected 3 Power Change: 0 = No change in power source 1 = Change detected 2 Low Battery 2 Condition: 0 = Condition not detected 1 = Detected 1 Low Battery 1 Condition: 0 = Condition not detected 1 = Detected 0 Control Point Detect: 0 = No Control Point detected 1 = Control Point detected I/O Address 3865h, R/W Keyboard Address 8025h, R/W-Clear only BIT FUNCTION -------------- 7 SMI REQ Mask 6 Pop-Up Timeout Mask 5 EBOX_ACT Mask 4 KEY_SEQ Mask 3 Power Chang Mask 2 Low Battery 2 Condition Mask 1 Low Battery 1 Condition Mask 0 Control Point Detect Mask All mask bits: 0 = SMI source is masked 1 = SMI source is un-masked Miscellaneous Options Register, I/O Address 3465h, Read/Write This 8 bit register is used by the microprocessor and the keyboard controller (keyboard address 8026h, read only) to select (or completely mask) the interrupt (IRQn) to be used for the digitizer FIFO. I/O Address 3465h, R/W Keyboard Address 8026h, RO BIT FUNCTION -------------- 7,6 Digitizer FIFO Interrupt Select 00 = IRQ5 01 = IRQ7 10 = IRQ9 11 = IRQ15 5 Digitizer Interrupt Map Enable. 0 = IRQ disabled 1 = IRQ enabled 4 Reserved 3 Force Disk Change 0 = Disk change clear enable 1 = Indicate disk change 2 SLOTON 0 = Option slot off 1 = Option slot on 1 EN IRQ12 0 = Enable mouse interrupt on IRQ12 1 = Disable mouse interrupt on IRQ12 0 PM Beep 0 = Enable beeps 1 = Disable beeps Digitizer FIFO Input Register, Keyboard Address 8006h, Write Only This 8 bit register serves as the digitizer data FIFO input port that is written to by the digitizer. Each byte written to this register increments the FIFO write pointer. When a packet has been written through the register, an interrupt (IRQn) is generated to the system (micro)processor, which will then read the FIFO. INT0 Source/Mask Registers, Keyboard Address 8007h, 8008h, Write Only These 8 bit registers determine the generation of the INT0 to the keyboard controller as the result of a "buffer full" condition of various functions, including the digitizer. When a source writes to a buffer, that buffer's corresponding flag in the source register (8007h) is set. If a set flag's corresponding mask bit in the mask register (8008h) is cleared, then INT0 to the keyboard controller becomes active. Keyboard Address 8007h, R/W BIT FUNCTION -------------- 7 Numeric Keypad Flag. 6 Secondary System to Keyboard Buffer Flag. 5 Reserved. 4 Serial Device Flag. 3 Timer Flag. 2 Keyboard Matrix Flag. 1 Input Buffer Full Flag. 0 Primary System to Keyboard Buffer Flag. All source bits: 0 = No INT0 source condition 1 = INT0 source condition exists Keyboard Address 8008h, R/W BIT FUNCTION -------------- 7 Numeric Keypad Mask 6 Secondary System to Keyboard Buffer Mask. 5 Reserved. 4 Serial Device Mask. 3 Timer Mask. 2 Keyboard Matrix Mask. 1 Input Buffer Full Mask. 0 Primary System to Keyboard Buffer Mask. All mask bits: 0 = INT0 source is masked 1 = INT0 source is un-masked ===== A further note from the Sysop == There is a section that I sent you that explains how it works. It's interfaced to an 8051 like a PS/2 style mouse is. It transfers serial data like a mouse or keyboard would through a keyboard controller chip ( 8051 ). One thing that wasn't included is the data stream. The digitizer interface sends out a 5 byte data stream that is defined below: Byte 0 bit 7, 0 = Pen out of grid range 1= Pen in grid range bit 6 - 2 RESERVED bit 1, 0= Barrel switch not depressed 1=Barrel switch depressed bit0, 0=Pen tip down 1=Pen tip up Byte 1 = MSB X location Byte 2 = LSB X location Byte 3 = MSB Y location Byte 4 = LSB Y location. ====== --- Ken Mandelberg | km@mathcs.emory.edu PREFERRED Emory University | {rutgers,gatech}!emory!km UUCP Dept of Math and CS | km@emory.bitnet NON-DOMAIN BITNET Atlanta, GA 30322 | Phone: Voice (404) 727-7963, FAX 727-5611